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| X25F032资料 | |
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X25F032 PDF Download |
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File Size : 116 KB
Manufacturer:XICOR Description:When interpolating, the user should normally bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. The chip will then continue to accept data on alternate rising edges of CLK. The user may leave SYNC LOW or change its value once per clock cycle, with equivalent results. The chip can be powered up and operated with SYNC grounded, but the input-to-output latency may vary by 1/2 input sample period and the host system wont know which (even- or odd-numbered) CLK rising edges strobe the input register. The setup and hold tim- ing requirements for SYNC, with respect to the rising edges of CLK, are the same as those for all other data and control inputs except OE, which is asynchronous. In two-channel mode, it must remain low after the first incoming data value. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：X25F032 厂 家：XICOR 封 装：SOP-8 批 号：08+ 数 量：512 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
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| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
