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| W78E51B-24资料 | |
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W78E51B-24 PDF Download |
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File Size : 116 KB
Manufacturer:Winbond Description:Reset Input (RP). The Reset input provides hardware reset of the Flash chip. Reset of the Flash memory is achieved by pulling RP to VIL for at least t PLPX. When the reset pulse is given, if the Flash memory is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the Flash memory is in Erase or Program mode the reset will take tPLYH during which the Ready/ Busy (RB) signal will be held at VIL. The end of the Flash memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being pro- grammed or the block(s) being erased. See Table 17 and Figure 9. Ready/Busy Output (RB). Ready/Busy is an open-drain output of the Flash chip. It gives the in- ternal state of the Program/Erase Controller (P/ E.C.) of the Flash device. When RB is Low, the Flash device is busy with a Program or Erase op- eration and it will not accept any additional pro- gram or erase instructions except the Erase Suspend instruction. When RB is High, the Flash device is ready for any Read, Program or Erase operation. The RB will also be High when the Flash memory is put in Erase Suspend or Standby modes. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：W78E51B-24 厂 家：Winbond 封 装：DIP40 批 号：06+ 数 量：4250 说 明：绝对原厂原装现货热卖！！ |
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运 费： 所在地：深圳 新旧程度： |
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