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| UDN2982LW资料 | |
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UDN2982LW PDF Download |
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File Size : 116 KB
Manufacturer:ALLEGRO Description:The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：UDN2982LW 厂 家：ALLEGRO 封 装：SOP-16 批 号：07+ 数 量：515 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
| 电 话：0755-83605789 |
| 手 机：13428979109 |
| QQ：656259901,307704921 |
| MSN：chenqiongxia18@126.com |
| 传 真：0755-23816523 |
| EMail：656259901@qq.com |
| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
