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| TA7299P资料 | |
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TA7299P PDF Download |
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File Size : 116 KB
Manufacturer:TOS Description: C Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. Instruction and data caches are two-way, set-associative, physically addressed, LRU replacement, and lockable on-line granularity. MMUs with 32-entry TLB, fully associative instruction, and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups Advanced on-chip-emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Operates at up to 80 MHz Memory controller (eight banks) Contains complete dynamic RAM (DRAM) controller Each bank can be a chip select or RAS to support a DRAM bank Up to 15 wait states programmable per memory bank Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices. DRAM controller programmable to support most size and speed memory interfaces Four CAS lines, four WE lines, one OE line Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) Variable block sizes (32 Kbyte to 256 Mbyte) Selectable write protection On-chip bus arbitration logic General-purpose timers Four 16-bit timers or two 32-bit timers Gate mode can enable/disable counting Interrupt can be masked on reference match and event capture System integration unit (SIU) Bus monitor Software watchdog Periodic interrupt timer (PIT) Low-power stop mode Clock synthesizer |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TA7299P 厂 家：TOS 封 装：DIP 批 号：07+ 数 量：1650 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
| 电 话：0755-83605789 |
| 手 机：13428979109 |
| QQ：656259901,307704921 |
| MSN：chenqiongxia18@126.com |
| 传 真：0755-23816523 |
| EMail：656259901@qq.com |
| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
