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| PAP1302LM资料 | |
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PAP1302LM PDF Download |
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File Size : 116 KB
Manufacturer:PXI Description:PAP1302LM is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：PAP1302LM 厂 家：PXI 封 装：BGA 批 号：08+ 数 量：4160 说 明：绝对原厂原装现货热卖！！ |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
| 电 话：0755-83605789 |
| 手 机：13428979109 |
| QQ：656259901,307704921 |
| MSN：chenqiongxia18@126.com |
| 传 真：0755-23816523 |
| EMail：656259901@qq.com |
| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
