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| NJM2903资料 | |
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NJM2903 PDF Download |
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File Size : 116 KB
Manufacturer:JRC Description:All inputs to the 626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs, DQ0C DQ15, also are referenced to the rising edge of CLK. The 626162 has two banks that are accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh both banks alternately. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：NJM2903 厂 家：JRC 封 装：SOIC-8 批 号：08+ 数 量：8418 说 明：绝对原厂原装现货热卖！！ |
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运 费： 所在地：深圳 新旧程度： |
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