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| MTC20154TQC资料 | |
|   | MTC20154TQC PDF Download | 
| File Size : 116 KB Manufacturer:ST Description:The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one- half-clock-cycle data transfers at the I/O pins. | |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
| 型 号:MTC20154TQC 厂 家:ST 封 装:QFP64 批 号:08+ 数 量:2000 说 明:绝对原厂原装现货热卖!! | |||||
| 运  费: 所在地:深圳 新旧程度: | |||||
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