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MC145167DW资料 | |
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MC145167DW PDF Download |
File Size : 116 KB
Manufacturer:MOTOROLA Description:Most Significant Data Bit (MSB). Data Bits 1C10. Least Significant Data Bit (LSB). No Internal Connection. Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. Analog Supply Voltage (+2.7 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:MC145167DW 厂 家:MOTOROLA 封 装:SOP 批 号:07+ 数 量:2502 说 明:100%真实库存,原装,部分现货 |
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运 费: 所在地:深圳 新旧程度: |
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联系人:陈小姐 |
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公司地址: 广东深圳市福田区华强北(振华路)赛格高科德电子市场A1848室 |