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LT1442CS资料 | |
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LT1442CS PDF Download |
File Size : 116 KB
Manufacturer:LT Description:Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. |
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1PCS | 100PCS | 1K | 10K | ||
价 格 | |||||
型 号:LT1442CS 厂 家:LT 封 装:SOP 批 号:08+ 数 量:1151 说 明:100%真实库存,原装,部分现货 |
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运 费: 所在地:深圳 新旧程度: |
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