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| EPM7128SQC160-15资料 | |
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EPM7128SQC160-15 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description: NOTES Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1.6V. 2See timing diagram below and Serial Interface section of this data sheet. 3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V. 4Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5Minimum time between read command and data read for all registers except WAVFORM register. For WAVFORM register t 9 =500ns min |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPM7128SQC160-15 厂 家：ALTERA 封 装：QFP 批 号：07+ 数 量：1400 说 明：100%真实库存，原装，部分现货 |
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