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| EPF1K30TC144-3资料 | |
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EPF1K30TC144-3 PDF Download |
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File Size : 116 KB
Manufacturer:ALTERA Description: The IDT72V8985 microprocessor port is a non-multiplexed bus architec- ture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control Registers, Connection Memory Low, Connection Memory High, and the Data Memory. All locations are read/written except for the Data Memory, which can be read only. Accesses from the microport to the Connection Memory and the Data Memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). In the IDT72V8985 device, the DTA output provides a maximum acknowledgment delay of 800ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Processor Mode), the maximum acknowledgment delay can be 1220ns. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：EPF1K30TC144-3 厂 家：ALTERA 封 装：QFP 批 号：08+ 数 量：1200 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
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