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| AT89C2051-24SU资料 | |
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AT89C2051-24SU PDF Download |
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File Size : 116 KB
Manufacturer:ATMEL Description:The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are linked together by 1 bits in the least significant bit (LSB) position of the instructions. The instructions that are chained together for simultaneous execution (up to eight in total) compose an execute packet. A 0 in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：AT89C2051-24SU 厂 家：ATMEL 封 装：SOP20 批 号：07+ 数 量：1499 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
| 电 话：0755-83605789 |
| 手 机：13428979109 |
| QQ：656259901,307704921 |
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| 传 真：0755-23816523 |
| EMail：656259901@qq.com |
| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
