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| ALS1005DR资料 | |
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ALS1005DR PDF Download |
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File Size : 116 KB
Manufacturer:TI Description:Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture One Instruction/Clock Execution Core Clock Rate is: 80960JA/JF 1x the Bus Clock ALS1005DR 2x the Bus Clock ALS1005DR 3x the Bus Clock Load/Store Programming Model Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers (8 sets) Nine Addressing Modes User/Supervisor Protection Model Two-Way Set Associative Instruction Cache 80960JA - 2 Kbyte ALS1005DR/JD - 4 Kbyte ALS1005DR - 16 Kbyte Programmable Cache-Locking Mechanism Direct Mapped Data Cache 80960JA - 1 Kbyte ALS1005DR/JD - 2 Kbyte ALS1005DR - 4 Kbyte Write Through Operation On-Chip Stack Frame Cache Seven Register Sets Can Be Saved Automatic Allocation on Call/Return 0-7 Frames Reserved for High-Priority Interrupts |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：ALS1005DR 厂 家：TI 封 装：SOP-14 批 号：07+ 数 量：2660 说 明：100%真实库存，原装，部分现货 |
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运 费： 所在地：深圳 新旧程度： |
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