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| AD5541JRZ资料 | |
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AD5541JRZ PDF Download |
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File Size : 116 KB
Manufacturer:AD Description: All min/max limits for the PD interface are production tested at +85C (extended grade)/+70C (commercial grade). Limits at +25C and -40C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25C and +85C (extended grade)/+70C (commercial grade). Limits at -40C are guaranteed by design, unless otherwise noted. Note 2: The input offset current is illustrated in Figure 1. Note 3: Effective differential input resistance is defined as the differential resistance between GND and VEE without any external resistance. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the PD Classification Mode section. RDISC and RCL must be 100ppm or better. Note 6: See Thermal Dissipation section for details. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (1%), the turn- on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage. Note 8: When the VUVLO is below VTH, G, UVLO, the MAX5942_ sets the turn-on voltage threshold internally (VUVLO,ON). Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY will not cause the MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: PGOOD references to OUT while PGOOD references to VEE. Note 11: Guaranteed by design. |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：AD5541JRZ 厂 家：AD 封 装： 批 号：08+ 数 量：5000 说 明：绝对原厂原封装正品 |
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运 费： 所在地：深圳 新旧程度： |
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| 联系人：陈小姐 |
| 电 话：0755-83605789 |
| 手 机：13428979109 |
| QQ：656259901,307704921 |
| MSN：chenqiongxia18@126.com |
| 传 真：0755-23816523 |
| EMail：656259901@qq.com |
| 公司地址： 广东深圳市福田区华强北（振华路）赛格高科德电子市场A1848室 |
